| 摘要 |
PURPOSE:To obtain a 4B-3T code converting circuit which does not cause malfunction to decide by majority, without making an error of 1-bit generated on a transmission line greater than 2-bit, by scattering codes causing errors to be parted >=4-bit. CONSTITUTION:When a code train is inputted from an input terminal 16, a sequential 4-bit code is stored in 1-bit storage circuits 17-20, and in transferring the content of storage to one-bit storage circuits 21-24 at each 4-bit, data of 4-bit intervals of the code train is sequentially stored to the circuits 21-24. When 4-bit delay circuits 25-30 connected to the storage circuis 21-23 respectively execute bit delay of 12, 8, 4, a data is inputted to input points J-M of a converting circuit 31, 4B-3T code conversion is performed with the combination of codes and converted into pulses of + and - polarity, and transmitted to a transmission line. At the reception side, reproduction is peformed with the inversion and a 4-bit delay circuit. In passing through the transmission line, the pulse section in 3-bit can be corresponded to the combination of codes in 5-bit intervals. |
