| 摘要 |
PURPOSE:To reduce the delay time in determining the integrating value, by making arithmetic directly the sum between the integrating value so far and the polarity sum in a ternary word produced through conversion, from a binary data. CONSTITUTION:A binary data in 4-bit converted into a parallel signal in a serial/parallel converting circuit 1 is inputted to an integrating value circuit 6, which operates directly an integrating value after the conversion into a ternary word, i.e., the sum between the integrating value I0 so far and the polarity sum in the ternary word produced after conversion from the binary data and inputs the sum into a code converting circuit 2. The code converting circuit 2 converts code between the inputted binary word and an outputted ternary word according to the mode determined by the integrating value, and generates and outputs the ternary word via a parallel/serial converting circuit and a binary-ternary value converting circuit 4. Thus, the loop delay is only the delay by the integrating circuit 4. |
