发明名称 PROTOCOL LOGIC VERIFICATION SYSTEM INCLUDING INFINITE OVERFLOW DETECTION
摘要 PURPOSE:To attain logical verification even to a part of a protocol as well whose signal number is infinite by discriminating it as infinite overflow when the system state having the increase signal series of the signal state of the same channel appears so as to stop an extension. CONSTITUTION:A block 8 detects the state that the number of signals stored on a channel between processes is infinite, that is infinite overflow. The L value of state 0.1 of the process 1 is 1.0 and an unprocessed signal series of channels 1.2 are 1.0, 2.0. The L value of the state 0.9 of the process 1 is 1.5 and the unprocessed signals series of the channel 1.2 are 1.3, 2.3, 1.4, 2.4, 1.5, 2.4. Thus, after 0.9, the state transition series is repeated and the signal 1.2 is stored, then it is discriminated as the infinite overflow. Similarly, the state 0.7 of the process 2 is marked by the type 3. Thus, acyclic state extension to the protocol is stopped.
申请公布号 JPS61191145(A) 申请公布日期 1986.08.25
申请号 JP19850030208 申请日期 1985.02.20
申请人 KOKUSAI DENSHIN DENWA CO LTD <KDD> 发明人 TSUNODA YOSHIAKI;WAKAHARA YASUSHI;NORIKOSHI MASAMITSU
分类号 H04L29/14;G06F11/28;G06F13/00;H04L13/00;H04L29/06 主分类号 H04L29/14
代理机构 代理人
主权项
地址