| 摘要 |
PURPOSE:To enable a operation test in a short time, by supplying a clock signal with a specified cycle into a required logical circuit block when no test mode signal is inputted while a clock signal with the cycle suitable for a test set externally is supplied into each logical circuit block when a test mode signal is inputted. CONSTITUTION:Clocks signals CL1-CL4 to be supplied to logical circuit blocks 1-4 are generated with a base clock generation circuit 6, a selection circuit 7 and counting circuits 8-11. To carry out an operation test for the blocks 1-4, an external clock signal TCL is fed to the circuit 7 and test mode signals TM are inputted into the circuit 7 and the circuits 8-11. Then, when no signal TM is inputted, signals CL1-CL4 supplied to blocks 1-4 from circuits 8-11 have cycle T1-T4 respectively while when a signal TM is inputted, they are the same in the cycle T5 as that of the signal TCL set to be all suited to the operation test. Thus, the operation test can be done for the blocks 1-4 at the cycle T5.
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