发明名称 SYNCHRONIZING SYSTEM FOR DIGITAL SIGNAL
摘要 <p>PURPOSE:To synchronize efficiently a digital signal of an optional bit rate by dividing a signal into a synchronizing part and an asynchronizing part and coding the asynchronizing part only into a code corresponding to 1, 0 and Empty and synthesizing the result with the synchronizing part. CONSTITUTION:An original signal S0 is fed to an input terminal (a) of a buffer memory 1. A written signal is read by a read pulse CR fed to a terminal (d) of the buffer memory 1.A read signal S1 is synthesized with a red command pulse at an OR gate 2 and a coded pulse train S is obtained. The read command pulse is delayed by a delay line 3 to instruct the presence of transfer. When the storage content of the buffer memory is 1 or below, an Empty signal E is outputted to a terminal (l) of the buffer memory 1. Thus, a continuous digital signal is synchronized efficiently into an optional bit rate.</p>
申请公布号 JPS6290047(A) 申请公布日期 1987.04.24
申请号 JP19850228675 申请日期 1985.10.16
申请人 HITACHI LTD 发明人 TAKASAKI YOSHITAKA
分类号 H04J3/06;H04J3/07;H04L25/05;H04N7/52 主分类号 H04J3/06
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