Interrupt synchronizing circuit

摘要

A synchronizing circuit that synchronizes the non-maskable interrupt (NMI) input signals of two separate microprocessor subsystems that are running synchronously as part of a fault tolerant computer system. This circuit enables both microprocessors to detect and respond to an error condition at an identical point in their relative bus timing sequence even though there may be a real time skew between the bus timing of these two subsystems. Storage and gating circuitry are used to provide the precise timing signals required for such synchronization.