| 摘要 |
This detector being applied to N multiplexed binary signals S1 t, S2 t, ..., SN t, each binary signal Si t being constituted by a series of blocks each comprising a set of data bits followed by a parity bit, two consecutive bits of the same block of a signal Si t being separated by m bits in the multiplexed signal, the said parity detector being characterised in that it comprises: - a parity calculating means 20, 24 comprising a first and a second input, the said multiplexed digital signal S t being applied to the said first input, the said calculating means delivering a signal R t, each bit of which is representative of the parity of the bits applied on the two inputs, - a delay means 22, 26, 261 -26N comprising an input linked to the output of the parity calculating means and an output linked to the second input of the parity calculating means, producing a delay of mT where T is the length of a bit cell of the signal S t. <IMAGE>
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