| 摘要 |
PURPOSE:To contrive the prevention of the malfunction of the titled circuit by varying an output signal of the input buffer having a high logic threshold voltage in the input buffer circuit where two kinds of the input buffers share one input terminal only when an input voltage over the threshold voltage is inputted for a prescribed time consecutively. CONSTITUTION:An output signal 5 is obtained from the 2nd input buffer 2 whose output is changed by a signal 4 inputted from an input terminal 4 in excess of a high threshold voltage 8. A delay circuit 11 is a circuit retarding its output signal by a time td with respect to the input signal, from which an output signal 9 is obtained. Then the signals 5, 9 are ANDed by an AND gate 12 and an 'H' signal appears at the output 10 after a signal having a longer time than the time td is given from the input terminal 4. Thus, even when a pulsive voltage noise is inputted from the input terminal 4 at normal readout, the output signal 10 is unchanged and no malfunction takes place. |
