| 摘要 |
A SMPS controllable the switching of a power transistor using pulse outputs of PWM IC has a rising time improvement circuit and a falling time improvement circuit. The rising time improvement circuit comprises a high frequency transformer including primary and secondary coils, a forward feedback circuit including a switching transistor (Q1), a resistor (R1) and a diode (D2), and second FET (K2) for providing the forward bias driving pulse to a first primary coil (N1) using a negative pulse output of PWM IC. The falling time improvement circuit comprises a first PET (K1) controlled by the output of a trigger pulse section (1) and a second FET for providing the reverse bias driving pulse to the first primary coil using a positive pulse output of PWM IC. |
