| 摘要 |
Among other aspects, the present invention relates to a network comprising a plurality of interconnected core circuits (10) particularly arranged on several units (6), wherein each core circuit (10) comprises: an electronic array (8, 9) comprising a plurality of computing nodes (90) and a plurality of memory circuits (80) which is configured to receive incoming events, wherein each computing node (90) is configured to generate an event comprising a data packet when incoming events received by the respective computing node (90) satisfy a pre-defined criterion, and a circuit which is configured to append destination address and additional source information, particularly source core ID, to the respective data packet, and a local first router (R1) for providing intra-core connectivity and/or delivering events to intermediate level second router (R2) for inter-core connectivity and to higher level third router (R3) for inter-unit connectivity, and a broadcast driver (7) for broadcasting incoming events to all the memory circuits (80) in the core circuit (10) in parallel. |
