发明名称 |
Logic level control circuit. |
摘要 |
<p>A logic level control circuit prevents impact ionization in a CMOS integrated circuit. The substrate bias voltage of the CMOS integrated circuit is detected by the control circuit and a control signal is provided in response to the detected bias voltage. The bias voltage can be zero volts or negative five volts. If the bias voltage is zero volts, the control signal is a logic level one. If the bias voltage is negative five volts, the control signal is a logic level zero. The control signal is applied to the gate of at least one other controlled device on the integrated circuit for turning that controlled device on and off. The controlled device coupled to a further CMOS device and turning the controlled device on and off prevents impact ionization by allowing the controlled device to alternately divide a voltage level with the further CMOS device or be effectively removed from the circuit. <IMAGE></p> |
申请公布号 |
EP0486879(A2) |
申请公布日期 |
1992.05.27 |
申请号 |
EP19910118941 |
申请日期 |
1991.11.06 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
MAYES, MICHAEL KEITH |
分类号 |
G11C11/417;G11C11/413;H01L21/822;H01L27/04;H03K17/081;H03K17/10;H03K17/16;H03K17/687 |
主分类号 |
G11C11/417 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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