| 摘要 |
The circuit connects a multiplexer to a multitude of flip-flops, selectively specifies a test point of the multiplexer, and limits an input channel of the multiplexer. The circuit includes a switching control unit (10) which outputs a switching control signals according to system clock signal (SCLK), a switching selector (20) which selectively outputs an outputs signals (Pi-Pi+(n-1)) of test points, a multiplexer (30) which selectively outputs an actual ouptut signal (Pi) or switching selector (20) output signal. The switching control unit (10) includes flip-flops (FF50-FF5n). The switching selector (20) includes buffers (B1-Bn).
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