发明名称 Semiconductor integrated circuit
摘要 A second power supply line is connected to a first power supply line via an N-MOS transistor and has a second potential (Vcc-Vt). The second power supply line is grounded to a ground line via one of P-MOS transistors of a clamp circuit, one of N-MOS transistors of a decode switch, an N-MOS sense amplifier, and a common source line of sense amplifiers. Accordingly, even when a power supply potential negatively bumps, a ground potential flows from the second power supply line through a current path thus formed, and the potential of the second power supply line can follow the negative bump. Since the transistors forming the clamp circuit are of the P-MOS type, the data lines are electrically connected to the second power supply line, so that the data lines can follow the negative bump of the first power supply line. Accordingly, it is possible to provide a data line precharging system which can follow the negative bump of the power supply without deteriorating the sensitivity of the amplifier of the voltage detecting type.
申请公布号 US5642314(A) 申请公布日期 1997.06.24
申请号 US19960706196 申请日期 1996.08.30
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 YAMAUCHI, HIROYUKI
分类号 G11C5/14;G11C7/10;G11C11/409;G11C11/4091;G11C11/4096;(IPC1-7):G11C7/00 主分类号 G11C5/14
代理机构 代理人
主权项
地址