发明名称 Method for forming studs and interconnects in a multi-layered semiconductor device
摘要 A method of manufacturing a semiconductor device having a stud and interconnect in a dual damascene structure uses selective deposition. The method includes forming a trench including a first opening portion and a second opening portion in a dielectric layer, forming a first adhesion layer on a surface exposed by the first opening portion, forming a second adhesion layer on a surface exposed by the second opening portion, and selectively depositing a conductive material on the first adhesion layer and the second adhesion layer, wherein growth of the conductive material on the second adhesion layer starts after growth of the conductive material on the first adhesion layer has started. The first and second adhesion layers are of different materials.
申请公布号 US5689140(A) 申请公布日期 1997.11.18
申请号 US19960768394 申请日期 1996.12.18
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHODA, NAOHIRO
分类号 H01L21/28;H01L21/768;H01L23/522;H01L29/78;(IPC1-7):H01L23/48;H01L23/52;H01L29/40 主分类号 H01L21/28
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