| 摘要 |
A PLL circuit includes a sampling pulse generator and a loop circuit using a sample and hold circuit as a phase detector. The sampling pulse generator generates a sampling pulse signal at each level transition of an NRZ input signal. The sample and hold circuit samples a clock signal and hold a voltage signal corresponding to a voltage of the clock signal according to the sampling pulse signal. A voltage-controlled oscillator included in the loop circuit generates the clock signal whose frequency is controlled based on tho voltage signal received from the sample and hold circuit through a loop filter. The voltage signal remains at an appropriate level even when the NRZ input signal remains at the same level for a relatively long time. The sampling pulse generator includes a delay circuit for delaying the NRZ input signal and an exclusive-OR circuit receiving the NRZ input signal and the delayed signal.
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