发明名称 |
Clock frequency synthesis using delay-locked loop |
摘要 |
A circuit for synthesizing, from a first signal having a first frequency, a second signal having a second frequency. This synthesis includes using a delay locked loop in combination with a minimal amount of logic circuitry to generate a synthesized output signal which is completely deterministic and does not require any analog control.
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申请公布号 |
US5805003(A) |
申请公布日期 |
1998.09.08 |
申请号 |
US19970921420 |
申请日期 |
1997.08.29 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
HSU, CHUAN-DING ARTHUR |
分类号 |
H03K5/13;H03K5/156;H03L7/081;H03L7/16;(IPC1-7):H03K5/13;H03K5/159 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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