| 摘要 |
A memory array circuit has two memory sections. Each memory section has a matrix of column lines and row lines. A plurality of memory cells are arranged in the matrix, with each memory cell comprising a tunnel diode connected in series with a load, with a data node therebetween. The impedance characteristics of the tunnel diode and the load is such that at the data node, they intersect to form two or more points of stability. In one embodiment, a conventional access transistor is used to write data into and to read data out of the memory cell. In another embodiment an avalanche diode is used to write data into and to read data out of the memory cell.
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