发明名称 |
Data processing system having a cache and method therefor |
摘要 |
A data processing system (20) has a cache (26) that does not use a TAG array for storing a TAG address as in a conventional cache. The cache (26), according to one embodiment, uses a state machine (30) for transitioning the cache (26) to an active state in response to a change of flow instruction which is a short backward branch instruction of a predetermined displacement. The predetermined displacement is less than the number of entries in the cache (26), so the cache can remain active as long as the program is in a loop which can be contained entirely within the cache. A look ahead feature for the valid bit array is provided that associates the valid bit for a current instruction with a previous instruction, such that during a read of the cache, the valid bit for a next instruction is checked with the same index used to read the current instruction.
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申请公布号 |
US5893142(A) |
申请公布日期 |
1999.04.06 |
申请号 |
US19960748855 |
申请日期 |
1996.11.14 |
申请人 |
MOTOROLA INC. |
发明人 |
MOYER, WILLIAM C.;ARENDS, JOHN;LEE, LEA HWANG |
分类号 |
G06F9/38;G06F12/08;G06F12/12;(IPC1-7):G06F13/00 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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