发明名称 |
Column decoder configuration for a 1T/1C ferroelectric memory |
摘要 |
A column decoder cell layout for use in a 1T/1C ferroelectric memory array includes a first column decoder section having two input nodes for receiving a first input/output signal and a first inverted input/output signal, two output nodes for providing a first bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal, a second column decoder section having two input nodes for receiving a second input/output signal and a second inverted input/output signal, two output nodes for providing a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of the column decoder cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
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申请公布号 |
US5892728(A) |
申请公布日期 |
1999.04.06 |
申请号 |
US19970970454 |
申请日期 |
1997.11.14 |
申请人 |
RAMTRON INTERNATIONAL CORPORATION |
发明人 |
ALLEN, JUDITH E.;WILSON, DENNIS R.;PERKALIS, JOSEPH J. |
分类号 |
G11C7/06;G11C8/10;G11C11/22;H01L27/108;H01L27/115;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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