发明名称
摘要 PURPOSE:To minimize an error fluctuation of a phase difference and to obtain proper phase shift quantity information. CONSTITUTION:The circuit is provided With a variable delay circuit 2 receiving a baud rate clock (b) and a prescribed delay control signal (f) and delaying variably the baud rate clock (b) based on the prescribed delay control signal (f) to output a variable measured timing clock c' and with a delay quantity control circuit 5 generating the prescribed delay control signal (f) based on phase shift quantity information (d) to control the variable measured timing clock c' from the variable delay circuit 2. A phase quantity measurement circuit 3 measures the phase of a pi/4 shift QPSK signal (a) based on the variable measurement timing depending on the said variable measured timing clock c' to obtain the phase shift quantity information (d) from the pi/4 shift QPSK signal (a) between adjacent variable measurement timings.
申请公布号 JP2885254(B2) 申请公布日期 1999.04.19
申请号 JP19910267379 申请日期 1991.10.16
申请人 NIPPON DENKI KK 发明人 NOBUSAWA HIDEAKI
分类号 H04L27/22 主分类号 H04L27/22
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