发明名称 SHARED MEMORY CONTROLLER USING MULTIPLEX TRANSMISSION LINE
摘要 PROBLEM TO BE SOLVED: To provide a highly reliable shared memory controller utilizing high- speed multiplex transmission lines. SOLUTION: In an access from transmission lines IFs 3a and 3b, the occupying bus master of a buffer 4 is judged in a buffer control part 5 and exclusive control is performed. Also, after a bus IF 6 confirms the soundness of a reception frame, a memory IF 7 performs transfer to a memory 9.
申请公布号 JP2000076174(A) 申请公布日期 2000.03.14
申请号 JP19980241344 申请日期 1998.08.27
申请人 HITACHI LTD 发明人 YAMADA TSUTOMU;OKURA TAKANORI;KUROSAWA KENICHI
分类号 G06F13/18;(IPC1-7):G06F13/18 主分类号 G06F13/18
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