发明名称 A/D CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain a parallel operation type A/D converter where a high speed operation and high precision can be realized. SOLUTION: An offset cancellation circuit 5 that detects an offset and generates a cancellation signal in response to the offset is provided independently to each voltage comparator circuit 4. The voltage comparator circuit 4 compares a signal voltage 4IN with a reference voltage 4REF and adds an inverted offset to the offset based on an offset cancellation signal 5OFC to cancel the offset of the input to the comparator circuit. A voltage division circuit 2 generates the reference voltage. Switch circuits SW1, SW2 apply a signal voltage to a reference voltage input terminal and a signal voltage input terminal of each voltage comparator circuit for an offset detection period and the voltage comparator circuit outputs a comparison result in response to the input offset. The offset cancellation circuit generates the offset cancellation signal on the basis of the comparison result.
申请公布号 JP2000165241(A) 申请公布日期 2000.06.16
申请号 JP19980332659 申请日期 1998.11.24
申请人 HITACHI LTD 发明人 TANBA HIROKO
分类号 G11B20/10;H03M1/14;H03M1/36;(IPC1-7):H03M1/36 主分类号 G11B20/10
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