| 摘要 |
PURPOSE: A floating bitline timer allowing a shared equalizer DRAM sense amplifier is provided to properly operate with a single equalizer circuit without causing an excessive current demand on the bitline equalization voltage source. Thus, the invention reduces the cost, complexity and the space required for a sense amplifier. CONSTITUTION: A dynamic random access memory chip comprising: memory element arrays having bitlines; a sense amplifier shared by the arrays, the sense amplifier including multiplexors(104) connected to the bitlines, and an equalizer circuit connected to the multiplexors(104); and a timer circuit(201) connecting first bitlines of the bitlines to the sense amplifier a time period after second bitlines of the bitlines are sensed by the amplifier, wherein the time period is less than an active phase of a row cycle of the bitlines.
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