发明名称 INTEGRATED CIRCUIT AND ESTIMATION METHOD THEREOF
摘要 PROBLEM TO BE SOLVED: To realize a simplification of the estimation of an integrated circuit performing transmitting/receiving of a high-speed signal hard to confirm its operation, and to prevent cost increase of the integrated circuit. SOLUTION: This integrated circuit is provided with a temporal axis extension circuit 3 in addition to a driver circuit 2 outputting the signal to the outside. The time base extension circuit 3 has an equivalent receiver circuit 6' similar to a conventional receiver circuit, and a D-type flip-flop 4 connected to the equivalent receiver circuit 6'. Input signals from pins P2, N2 of the time base extension circuit 3 are inputted to gates of CMOS transistors M4, M3 in the equivalent receiver circuit 6', and an equivalent differential reception signal (P3/N4) outputted from drains of the transistors M3, M4 is inputted to a D input of the D-type flip-flop 4. A measurement clock CK1 is inputted to a clock input of the D-type flip-flop 4, and an extension signal VEPD is outputted to a terminal of the time base extension circuit 3 from a Q output of the D-type flip-flop 4.
申请公布号 JP2001141783(A) 申请公布日期 2001.05.25
申请号 JP19990318923 申请日期 1999.11.09
申请人 CANON INC 发明人 KAWASAKI MOTOAKI;IZEKI MASAMI
分类号 G01R31/28;G01R31/319;H01L21/822;H01L27/04;H03K19/00;(IPC1-7):G01R31/28 主分类号 G01R31/28
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