发明名称 INTEGRATED CIRCUIT AND ITS DESIGN METHOD
摘要 PROBLEM TO BE SOLVED: To facilitate a test of a boundary area between blocks of a device made by combining a block made up of a combination of standard cells with a custom block made up of a macro block and an IP. SOLUTION: The custom block CB1 is designed, with a means added thereto for performing computations, such as EXOR computation simpler than usual operation and outputting it when the block CB1 is put into scan mode. This simplifies logical relations between input and output, without being affected by the history of data in the past stored in memories and registers contained in the block CB1. Similarly to the standard cell block SCB1 using a scan method, test patterns can be produced automatically by ATPG.
申请公布号 JP2001183424(A) 申请公布日期 2001.07.06
申请号 JP19990370443 申请日期 1999.12.27
申请人 TOSHIBA CORP 发明人 MORI JUNJI
分类号 G01R31/28;G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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