| 摘要 |
PURPOSE: An address input buffer control circuit is provided to execute various operating modes with one mask set by adding a byte selection signal and a fuse option. CONSTITUTION: An upper and a lower byte signal portion(100,200) receive input signals from the outside and output an upper and a lower byte signal. A chip selection signal portion(300) outputs a chip selection signal. A byte selection signal portion(400) outputs a byte selection signal. The first and the second fuse portions(500,600) outputs the first and the second fuse signals. An address enable portion(700) outputs an address control enable signal in response to the byte selection signal and the fuse selection signal. An address control portion(800) outputs an address control signal by an address upper and lower byte signal in response to the chip selection signal and the address control enable signal. A chip drive control portion(900) outputs a chip drive signal in response to the address control signal and the chip selection signal.
|
