| 摘要 |
PROBLEM TO BE SOLVED: To reduce number of address signal lines by transmitting a part of address signal through data signal lines. SOLUTION: An address signal consisting of 23 bits is transmitted from a CPU 20 to a memory control circuit 40, and the high order 2 bits of the address signal is a row address signal. The row address signal is transmitted through a data signal line 24 and held in a register 42, and only the remaining 21 bits of the address signal is transmitted through an address signal line 22. The memory control circuit 40 generates a row address signal of 14 bits and a column address signal of 9 bits from the address signal held in a register 42 and an address signal transmitted through the address signal line 22, and accesses SDRAM 30 based on this row address signal and the column address signal.
|
