发明名称 FAILSAFE DETECTION SYSTEM AND METHOD FOR DIFFERENTIAL RECEIVER CIRCUITS
摘要 PROBLEM TO BE SOLVED: To provide an apparatus for providing failsafe detection for a differential receiver. SOLUTION: Comparators 205, 210 are used to detect a differential voltage created by offset voltage resistor of a differential receiver device. The output of a NAND gate 220 is high when there is value data on the bus and low when a data signal is below a predetermined failsafe threshold. However, the output of the NAND gate 220 is delayed to an OR gate 240 by a predetermined period. A delay device 650 keeps a glitch or premature toggle from occurring when failsafe is detected. The delay caused by the delay device 650 should be longer than the substantial delay passing through an XOR gate 640 and an activity timer 230. If the delay device 650 were not present, the failsafe condition would be transmitted to the Failsafe bit before causing the glitch.
申请公布号 JP2003008418(A) 申请公布日期 2003.01.10
申请号 JP20020084841 申请日期 2002.03.26
申请人 TEXAS INSTR INC <TI> 发明人 TINSLEY STEVEN J;HWANG JULIE;MORGAN MARK W
分类号 H03K19/007;H04L25/02;H04L25/08;(IPC1-7):H03K19/007 主分类号 H03K19/007
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