发明名称 PARALLEL-SERIAL CONVERSION CIRCUIT, SERIAL DATA GENERATING CIRCUIT, SYNCHRONIZING SIGNAL GENERATING CIRCUIT, CLOCK SIGNAL GENERATING CIRCUIT, SERIAL DATA TRANSMISSION APPARATUS, SERIAL DATA RECEIVER, AND SERIAL DATA TRANSMISSION SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a parallel-serial conversion circuit capable of transmitting serial data without the need for a transmission path for a bit delimiter signal with low power consumption while preventing the circuit scale from being increased. SOLUTION: The parallel-serial conversion circuit is provided with: a first shift register 1 for outputting positive serial data while bit-shifting received positive parallel data in response to a shift clock signal; a second shift register 2 for outputting negative serial data while bit-shifting negative parallel data resulting from bit-inverting the positive parallel data in response to the shift clock signal, a first pulse generating circuit 20 for outputting a first pulse signal in response to the positive serial data; a second pulse generating circuit 21 for outputting a second pulse signal in response to the negative serial data; and a composite circuit 5 for composing the first and second pulse signals, and the parallel-serial conversion circuit uses a composite signal for the shift clock signal. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004032217(A) 申请公布日期 2004.01.29
申请号 JP20020183704 申请日期 2002.06.24
申请人 SHARP CORP 发明人 HATTORI SHINJI
分类号 H03M9/00;H04L25/02;(IPC1-7):H03M9/00 主分类号 H03M9/00
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