Method for manufacturing thin film transistor array panel

摘要

A thin film transistor array panel includes: a gate line on a substrate and including a gate electrode; a first gate insulating layer on the substrate and the gate line, the first gate insulting layer including a first portion adjacent to the gate line and a second portion overlapping the gate line and having a smaller thickness than that of the first portion; a second gate insulating layer on the first gate insulating layer; a semiconductor layer on the second gate insulating layer; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a passivation layer on the second gate insulating layer, the source electrode and the drain electrode; and a pixel electrode on the passivation layer and connected with the drain electrode. The first gate insulating layer and the second gate insulating layer have stress in opposite directions from each other.

主权项

1. A method for a thin film transistor array panel, comprising:
forming a gate line including a gate electrode, on a substrate; forming an insulating material layer on the substrate and on the gate line; forming a first gate insulating layer from the insulating material layer, comprising:
forming a first portion on the substrate and adjacent to the gate line,forming a second portion by removing a thickness portion of the insulating material layer overlapping the gate line, andforming a step portion connecting the first portion and the second portion,wherein a thickness of the second portion is smaller than a thickness of the first portion, forming a second gate insulating layer on the first gate insulating layer; forming a semiconductor layer on the second gate insulating layer; forming a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; forming a passivation layer on the second gate insulating layer, the source electrode and the drain electrode; and forming a pixel electrode connected with the drain electrode, on the passivation layer, wherein the first and second gate insulating layers are between the gate line and the semiconductor layer, the first gate insulating layer has a tensile stress, and the second gate insulating layer has a compressive stress.