Storage device write pulse control

摘要

According to an example, a method for storage device write pulse control may include writing a storage device to a first polarity by driving a row address line (RAL) and a column address line (CAL) to an intermediate voltage level RCA for a cycle A. The RAL may be driven to a voltage level RB for a cycle B pulse duration, and the CAL may be maintained at RCA for the cycle B pulse duration. The RAL may be driven to a voltage level RC for a cycle C pulse duration, and the CAL may be driven to a voltage level CC for the cycle C pulse duration. The RAL may be driven to RCA, and the CAL may be driven to a voltage level CD for a cycle D pulse duration. The RAL may be maintained at RCA, and the CAL may be driven to RCA.

主权项

1. A method for storage device write pulse control of a storage device of a plurality of storage devices of a storage array, the method comprising:
writing the storage device to a first polarity by:
driving a row address line and a column address line of the storage device to approximately an intermediate voltage level RCA for a cycle A;driving the row address line to a voltage level RB greater than the intermediate voltage level RCA for a predetermined cycle B pulse duration following the cycle A, and maintaining the column address line at approximately the intermediate voltage level RCA for the predetermined cycle B pulse duration;driving the row address line to a voltage level RC lower than the intermediate voltage level RCA for a predetermined cycle C pulse duration following the predetermined cycle B pulse duration, and driving the column address line to a voltage level CC higher than the intermediate voltage level RCA for the predetermined cycle C pulse duration to write the storage device to the first polarity;driving the row address line to approximately the intermediate voltage level RCA, and driving the column address line to a voltage level CD lower than the intermediate voltage level RCA for a predetermined cycle D pulse duration following the predetermined cycle C pulse duration; andmaintaining the row address line at approximately the intermediate voltage level RCA, and driving the column address line to approximately the intermediate voltage level RCA following the predetermined cycle D pulse duration.