发明名称 |
Multi level error correction system for high density memory |
摘要 |
This specification describes an error correction system for a high density memory made up of a number of monolithic wafers each containing a plurality of arrays that are addressed thru circuitry and wiring contained on that wafer. The storage bits on the wafers are functionally divided into a number of blocks each containing a plurality of words. The words of each block are on several wafers with each word made up of a plurality of arrays on a single array wafer. Each word in a block is protected by a similar error correction double multiple error detection code. The block is further protected by two additional check words made up using a b-adjacent code. Each byte in the check words protects one byte position of the words of the block. When a single error is detected in any word by the SEC-MED code the code corrects the error. If a multiple error is detected, the multiple error signal points to the word in error to be corrected by the b-adjacent code check words. |
申请公布号 |
US3893071(A) |
申请公布日期 |
1975.07.01 |
申请号 |
US19740498510 |
申请日期 |
1974.08.19 |
申请人 |
IBM CORPORATION |
发明人 |
BOSSEN, DOUGLAS C.;HSIAO, MU-YUE;PATEL, ARVIN M. |
分类号 |
G06F12/16;G06F11/10;(IPC1-7):H04L1/10;G11C29/00 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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