发明名称 System and method for the transmission of data and streams containing video data D<sub>video </sub>in a channel with given bitrate
摘要 System and method for multiplexing data Di and one or more streams containing video data Dvideo in a transmission channel with fixed bitrate comprising a multiplexer (11) and its controller (112), the multiplexer (11) comprising one to n inputs (11v) receiving the stream or streams Dvideo, a bitrate allocator (12), the multiplexer (11) comprises an input (11d) for the data Di to be multiplexed, and the said system comprises at least the following elements: a memory (20) receiving the data to be multiplexed with the stream or streams Dvideo, a bitrate estimator (21) which transmits a bitrate request Rd to the bitrate allocator (12), the bitrate request Rd is transmitted to the controller (112) of the multiplexer and delayed, the controller (112) is suitable for reading from the memory (20) the data Di to be multiplexed, up to compliance with the bitrate request Rd.
申请公布号 US9467719(B2) 申请公布日期 2016.10.11
申请号 US201414338591 申请日期 2014.07.23
申请人 HARMONIC INC. 发明人 Cognault Marc;Mosset Jean-Pierre;Le Mouel Franck
分类号 H04N21/00;H04N21/236;H04L5/00;H04L12/825;H04L29/06;H04N21/2365 主分类号 H04N21/00
代理机构 Meagher Emanuel Laks Goldberg & Liao, LLP 代理人 Meagher Emanuel Laks Goldberg & Liao, LLP
主权项 1. A system for multiplexing data (Di) and one or more streams containing video data (Dvideo) in a transmission channel with fixed bitrate comprising: at least one configuration interface; a multiplexer and its controller, the multiplexer comprising one to n inputs for receiving the one or more streams containing video data (Dvideo) and an input for receiving the data (Di) to be multiplexed, a bitrate allocator; a memo configured to receive the data (Di) to be multiplexed with the one or more streams containing video data (Dvideo); and a bitrate estimator configured to transmit a bitrate request (Rd) to the bitrate allocator, the bitrate request (Rd) is transmitted to the controller of the multiplexer, and the bitrate request (Rd) is delayed, wherein the controller is suitable for reading from the memory the data (Di) to be multiplexed, up to compliance with the bitrate request (Rd).
地址 San Jose CA US