Interrupt control system for a microcomputer

摘要

An interrupt control system for accepting and retaining a multiple of interrupt requests to a central processing unit of a microcomputer assigning a priority to each, generating an interrupt instruction, and a CPU interrupt signal including means for storing CPU register data and status flags upon receipt of said interrupt and restoring such data and flags when the interrupt task is complete. The control system also includes means for displaying certain data as controlled by the computer software program and for entering manual data.