Chip package structure and chip packaging method

摘要

Embodiments of the present invention provide a chip package structure and a chip packaging method, which is related to the field of electronic technologies, and can protect chips and effectively dissipate heat for chips. The chip package structure includes a substrate, chips, and a heat dissipating lid, where the chips include at least one master chip disposed on the substrate and at least one slave chip disposed on the substrate; the heat dissipating lid is bonded to the slave chip by using a heat conducting material, and the heat dissipating lid covers the at least one slave chip; and the heat dissipating lid includes a heat dissipating window at a position corresponding to the at least one master chip. The embodiments of the present invention are applicable to multi-chip packaging.

主权项

1. A chip package structure, comprising:
a substrate; at least one master chip disposed on the substrate and a plurality of slave chips disposed on the substrate in a stack; a heat dissipating lid bonded to a top one of the plurality of slave chips through a first heat conducting material, and covering the plurality of slave chips, the heat dissipating lid comprising a heat dissipating window at a position corresponding to the at least one master chip; and a heat sink comprising a boss structure, the boss structure located within the heat dissipating window and corresponding to a position of the at least one master chip, the heat sink bonded to the at least one master chip via the boss structure through a second heat conducting material on the at least one master chip at the heat dissipating window, and bonded to the heat dissipating lid through a third heat conducting material on the heat dissipating lid; wherein the heat dissipating lid comprises a first packaging strip that is located at edges proximal a first edge of a periphery of the heat dissipating lid and disposed on a substrate side, wherein the first packaging strip is bonded to the substrate by using a bonding material; a second packaging strip that is located at edges proximal a second edge of the periphery of the heat dissipating lid and disposed on the substrate side, the second packaging strip located between the plurality of slave chips and the master chip, wherein the second packaging strip is bonded to the substrate by using the bonding material.