Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer

摘要

A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer with a bottom opening is formed over the first blocking dielectric layer by deposition of a conformal material layer and an anisotropic etch. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched by an isotropic etch process that minimizes overetch into the substrate. An optional additional blocking dielectric layer, at least one charge storage element, a tunneling dielectric, and a semiconductor channel can be sequentially formed in the memory opening to provide a three-dimensional memory stack.

主权项

1. A method of fabricating a memory device, comprising:
forming a stack including an alternating plurality of material layers and insulator layers over a substrate; forming a memory opening extending through the stack; forming a first blocking dielectric layer in the memory opening and over the stack; forming a continuous material layer over the first blocking dielectric layer; forming a spacer by anisotropically etching the continuous material layer, wherein a top surface of a horizontal portion of the first blocking dielectric layer is physically exposed within an opening in the spacer; etching the horizontal portion of the first blocking dielectric layer at a bottom of the memory opening through the opening in the spacer, whereby a top semiconductor surface of the substrate is physically exposed at a bottom of the memory opening; forming a memory material layer comprising a charge trapping material or patterned conductive material portions over the top semiconductor surface of the substrate and over a sidewall of the spacer within the memory opening after the continuous material layer is patterned into the spacer; and forming a tunneling dielectric layer and a semiconductor channel over the memory material layer.