发明名称 |
SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE |
摘要 |
A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon). |
申请公布号 |
US2016372606(A1) |
申请公布日期 |
2016.12.22 |
申请号 |
US201615182812 |
申请日期 |
2016.06.15 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
ITO Daigo;MATSUBAYASHI Daisuke;NAGAI Masaharu;YAMAMOTO Yoshiaki;HAMADA Takashi;OKAZAKI Yutaka;SASAGAWA Shinya;KURATA Motomu;YAMADE Naoto |
分类号 |
H01L29/786;H01L27/12;H01L21/425;H01L21/46;H01L29/04;H01L29/66 |
主分类号 |
H01L29/786 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor device comprising:
a first insulating layer over a substrate; a first metal oxide layer over the first insulating layer; an oxide semiconductor layer over the first metal oxide layer; a second metal oxide layer over the oxide semiconductor layer; a gate insulating layer over the second metal oxide layer; and a gate electrode layer over the gate insulating layer, wherein the oxide semiconductor layer comprises a first region, a second region, and a third region, wherein the first region and the second region each comprise a region overlapping with the gate electrode layer, wherein the second region is between the first region and the third region, wherein the second region comprises a region with lower resistance than the first region, wherein the third region comprises a region with lower resistance than the second region, wherein the second region and the third region each comprise a region containing an element N, and wherein N is phosphorus, argon, or xenon. |
地址 |
Atsugi-shi JP |