| 摘要 |
PURPOSE:To reduce the occupied area on a chip in circuit integration, by inserting a level clamp circuit consisting of (n) pieces of MOS.FET between a connecting point of two internal buffer transistors (TR) and an output signal terminal. CONSTITUTION:Between a connecting point of internal output buffer TRs QB1 and QB2 consisting of n type enhancement EHMOS.FETQB1, QB2 and an output termina l, a level clamp circuit 3 consisting of (n) pieces of n type EHMOS. FETQ1-Qn is inserted. The drain of the Q1-Qn of the circuit 3 and the gate of the Q1 are connected to the terminal 1, the source of Qi (where; i=1-n) is connected to the gate of Qi+1, and the source of Qn is grounded. When a voltage VIN applied from the terminal 1 is smaller than or equal to the maximum rating VINMAX to the input voltage of the QB2, since the gate input voltage VGN of the Qn does not reach a threshold voltage VTHn of the Qn, the Qn turns off, and when VIN>VINMAX, VGN>THn is obtained, the Q1-Qn are all turned on and grounded, and since the QB1, QB2 are protected from an external failure voltage input, the QB1, QB2 can be made smaller. |
