| 摘要 |
PURPOSE:To decrease the number of external terminals for addresses by equipping a series-parallel converting circuit which supplies a high-order address in series in a chip, and specifying the high-order slow operation address in series through external terminals during address assignment. CONSTITUTION:For, for example, a 1M-word-x-1-bit RAM, the 1M-bit memory cell in a chip is divided into 128 pages of 8K words. The low-order address is inputted from 13 terminals A0-A12, decoded by an address decoder 6, and supplied to the memory cell 2. At the same time, the high-order 7-bit address 7 is inputted in series from a terminal SAD, and passed through a series-parallel converting circuit 4 driven by a clock from a clock terminal CK to obtain parallel 7-bit address information. Thus, the number of terminals for the high-order address is decreased and the total number of terminals is reduced to, for example, 22. |
