| 摘要 |
PURPOSE:To obtain a PLL which has a short lock-in time and a large lock-in range and to ensure a suitable application of the PLL to a device that always needs clocks, by securing an operation similar to a synchronous oscillation type PLL and at the same time generating the self-travelling power even in an unlocked state. CONSTITUTION:A capacity C1 is charged and discharged when a buffer B1 of a pump circuit 4' is on and a buffer B2 is on respectively. Both buffers B1 and B2 are turned off at one time with intervention of inhibit gates G1 and G2. These gates G1 and G2 are controlled with the Q output EBL (enable) of an FF6. Series resistances R2 and R3 are provided at an input stage of a VCO1' and have oscillations with a desired self-travelling frequency. A control signal CNT stops the locking of a PLL with H and locks the PLL with L respectively. A frequency divider 2' is repetitively reset while the signal CNT is kept at H. This reset is stopped when the first input IN arrives after the signal CNT is changed to L. Then the counting of the counter 2' is started, and at the same time the operation of the circuit 4' is started. At this time and thereafter, an output OUT synchronizes with an input IN in terms of phase. |
