| 摘要 |
PURPOSE:To obtain a simplified digital phase control circuit by providing a means which selects one of clock signals in response to a control signal and a means which generates an output clock signal with specific phase relation with an input data signal by using the selected clock signal. CONSTITUTION:A flip-flop 35 is set invariably in response to waveform-shaped data from a gate 28. A phase shifter 40 consists of a delay line circuit 41, multiplexer 42, and up/down counter 43. The delay line circuit 41 provides delay of 100+1sec in total by ten taps (T1, T2,...T9, and T10) and a relative delay increase which is 10% of the total delay amount equal to a reference clock period is obtained from each tap. The up/down counter 43 generates and sends a binary-coding selection address to a multiplexer 42, and consequently one output is selected among the 10 taps of the delay line circuit 41 to generate a reference clock pulse having a corresponding phase shift.
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