发明名称 VITERBI DECODER
摘要 PURPOSE:To make a minimum metric value node detection circuit unnecessary and to miniaturize a circuit scale, by obtaining an encoded output at every decoding cycle from a bit of maximum likelihood path information held at a trace storage part. CONSTITUTION:A path selection part 72 performs survival path selection by performing path metric arithmetic calculation and comparison of results, and outputs path selection signals SP1-SPn, and stores them on a path selection signal storage part 3 extending over path history length. A trace arithmetic part 74 finds the node information of maximum likelihood path by a mode switching signal MC, and stores it in a trace path storage part 75, and updates the information to the latest one. A decoding part 77 obtains the decoded output at every decoding cycle from the node information at the final stage of the maximum likelihood path held at the trace path storage part 75. The decoding of the decoder 77 is controlled so as to be performed for several times in one tracing cycle by a division control part 76.
申请公布号 JPS63153922(A) 申请公布日期 1988.06.27
申请号 JP19860300135 申请日期 1986.12.18
申请人 FUJITSU LTD 发明人 NAKAMURA TADASHI;YAMASHITA ATSUSHI
分类号 H03M13/00;H03M13/23 主分类号 H03M13/00
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