| 摘要 |
PURPOSE:To surely protect a stored data even when the runaway of a processor occurs, by providing the processor which generates an instruction to update the data of a data storage means, and a means which prohibits the updating of the data storage means by an update instruction until a prescribed signal is outputted from the processor. CONSTITUTION:AND gates 10 and 11 decode an A5H and a 5AH from the output of an address port in a CPU1, and are included in an address decoder 2. To clear a counter 14 by the CPU1, firstly, a C3H should be written on the address A5H, and next, a 3CH should be written on the address 5AH. Also, since a latch 7' is cleared when the counter 14 is cleared, to clear the counter 14 by the CPU1 following after clearing the counter 14 once, the C3H should be written again on the address A5H, and following that, the 3CH should be written on the address 5AH. Possibility to clear a WDT (watchdog timer) 4 during the runaway of the CPU1 is vary low. In such a way, it is nearly possible to prevent the data of the WDT4 from being cleared even when the runaway of the CPU1 occurs. |
