| 摘要 |
A microprocessor is provided with cage position detectors producing outputs representative of the position of the cage in any one of three sections; one section immediately above a normal floor arrival section, and another immediately below. A speed reference signal having a preferred characteristic is generated and an actual cage speed signal compared with the reference signal. The speed reference signal generator produces a reference signal increasing gradually at first and held fixed after reaching a predetermined value and terminating upon receiving an output signal indicating the cage floor is within the normal floor arrival section.
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