Power-on reset circuit

摘要

A Power-on Reset circuit is described. The Power-on Reset is formed by two comparators and a latch circuit. The Power-on Reset circuit will de-assert the reset state once the supply voltage reaches a first reference point and re-assert the reset state once the supply voltage drops below a second reference point. The Power-on Reset circuit disclosed further includes circuits to initialize properly and to ensure the regulator voltage and the bandgap voltages are stable and above the ground level voltage.

主权项

1. A power-on reset circuit that generates a reset signal, comprising:
a first comparator having a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a first reference voltage, and the second input terminal coupled to a supply voltage; a second comparator having a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to the supply voltage, and the second input terminal coupled to a second reference voltage; a latch circuit having a first terminal, a second terminal, and an output, wherein the output terminal of the first comparator is coupled to the first terminal, the output terminal of the second comparator is coupled to the second terminal, and the output of the latch circuit is configured to generate a de-assert signal to de-assert a reset state in response to the supply voltage increasing above the first reference voltage and is configured to generate a re-assert signal to re-assert the reset state in response to the supply voltage dropping below the second reference voltage; and a blocking circuit that blocks the de-assert signal prior to the reference voltages stabilizing.