| 摘要 |
PURPOSE:To protect erroneous operation of a system by preparing the system such that unless normal bit clock signal or data load signal is input, the output signal of a shift register cannot be ratched by a register. CONSTITUTION:When noise is mixed in a bit clock signal, since a counter 7 counts abnormally much, before a data load signal 5 reaches low level, a load enable signal 11 falls at low level, and when the data load signal 5 reaches low level, the load enable signal 11 goes up at high level. Further, when noise is mixed in the data load signal 5, since the data load signal 5 falls at low level before serial data signals are all transferred, the counter 7 is reset in the way of completing all the necessary counting. With this, the load enable signal 11 is left at high level and a clock signal 12 is also kept at high level. |
