ADDRESS BUS ARBITRATOR OF MULTIPROCESSOR SYSTEM

摘要

The arbitrator processes independent data transmission processes of several handlers without mutual interruption to improve the efficiency of bus. It includes a control logic of address bus arbitration (1) for controlling arbitration, a multiplexer (2) for applying request signal (req) to one of the signal lines (ABRQ0-ABRQ12), a priority encoder (4) for detecting the signal of the highest priority, a 4 bit comparator (5) for comparing the output of the priority encoder (4) with its slot address signal (3), and an equity flag (6) for being checked to maintain the equity of address bus usage.