DUAL-LOOP PROGRAMMABLE AND DIVIDERLESS CLOCK GENERATOR FOR ULTRA LOW POWER APPLICATIONS

摘要

A programmable clock generator is provided which is particularly suitable for low power applications. The programmable clock generator is comprised of: an oscillator circuit that generates an output signal whose frequency is set by a control signal, two feedback loops for controlling output frequency and a loop select that selects which feedback loop is operational at a given time. In operation, the frequency loop operates to coarsely adjust the frequency of the output signal; whereas, the phase loop operates to finely adjust the frequency of the output signal. The clock generator is preferably implemented by transistors operating in or near the subthreshold region.

主权项

1. A programmable clock generator, comprising:
an oscillator circuit configured to receive a control signal and generate an output signal oscillating at a frequency, where the frequency of the output signal is set in accordance with the control signal; a frequency-locked loop circuit configured to receive a desired output frequency and the output signal from oscillator circuit, wherein the frequency-locked loop circuit determines frequency of the output signal and generates an error signal without the use of a frequency divider, where the error signal indicates a difference between the desired output frequency and the determined output frequency; a phase-locked loop circuit configured to receive a reference signal and the output signal from oscillator circuit, wherein the phase-locked loop circuit determines a phase error between the reference signal and the output signal without the use of a frequency divider and generates an error signal from the phase error, where the error signal indicates a difference between the desired output frequency and the determined output frequency; a loop selector circuit configured to receive the error signal from the frequency-locked loop circuit and the error signal from the phase-locked loop circuit, wherein the loop selector circuit selects one of the error signals and outputs the selected error signal; and a controller configured to receive the selected error signal from the loop selector circuit and converts the error signal to the control signal for the oscillator circuit.