LOW CLOCKING POWER FLIP-FLOP

摘要

Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.

主权项

1. A flip-flop electronic circuit comprising:
a master latch coupled to a slave latch in a flip-flop configuration; and a clock control circuit for comparing an input to said master latch with an output of said slave latch, and responsive to said comparing, said master latch and said slave latch are configured to retain their respective states when said flip-flop electronic circuit is in a quiescent condition.