发明名称 |
ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE |
摘要 |
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region. |
申请公布号 |
US2016268390(A1) |
申请公布日期 |
2016.09.15 |
申请号 |
US201615159269 |
申请日期 |
2016.05.19 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHOU Anthony I.;KUMAR Arvind;LIN Chung-Hsun;NARASIMHA Shreesh;ORTOLLAND Claude;SHAW Jonathan T. |
分类号 |
H01L29/51;H01L29/423;H01L29/417;H01L29/78 |
主分类号 |
H01L29/51 |
代理机构 |
|
代理人 |
|
主权项 |
1. A gate structure comprising:
an interfacial dielectric layer on substrate, a source side and a drain side of the gate structure, the interfacial dielectric having a first thickness on the source side and a second thickness on the drain side, the first thickness being different than the second thickness forming an asymmetric gate dielectric; a gate material formed on the interfacial dielectric layer; sidewalls on the gate material on the source side and drain side; and high-k dielectric layer on the sidewalls on the drain side and underlying the gate material. |
地址 |
Armonk NY US |